1. Field of the Invention
The present invention is related to an on-chip noise filter circuit, and more particularly to a noise filter circuit for decoupling transient voltage being on power lines of an integrated circuit.
2. Description of the Related Art
An electrostatic discharge (ESD) event is an important reliability issue for integrated circuits (ICs). To meet component-level ESD reliability, on-chip ESD protection circuits are implemented in the I/O cells and power/ground cells of CMOS ICs. Besides the component-level ESD issue, the system-level ESD issue has been an increasingly significant reliability issue for CMOS IC products, which resulted from strict reliability test standard requirements, such as system-level ESD tests for electromagnetic compatibility (EMC) regulations. In general, an electrical product must sustain an ESD level of +8 kV under a contact-discharge test mode and +15 kV under an air-discharge test mode, so as to meet “level 4” immunity requirements. However, a high energy ESD will induce noise, thus causing damage or malfunction to CMOS ICs of electrical products. Furthermore, some CMOS ICs are very susceptible to system-level ESD stress, even though the CMOS ICs have passed the component-level ESD specifications, such as having a human-body-model (HBM) of ±2 kV, a machine-model (MM) of ±200V, and a charged-device-model (CDM) of ±1 kV.
For comprehensive component-level ESD verification, two ESD tests with a pin-to-pin ESD stress and a VDD-to-VSS ESD stress are performed to verify ESD reliability for an IC chip. The two ESD testing modes often lead to damage in internal/core circuits of IC chips, as some unanticipated ESD currents flow into the internal/core circuits through I/O pins and power lines. Therefore, a noise filter circuit coupled between VDD and VSS power lines is necessary for whole-chip ESD protection. The noise filter circuit can further provide a low impedance path between VDD and VSS power lines to efficiently discharge ESD current when an input (or output) pin is zapped under positive-to-VSS (PS-mode) or negative-to-VDD (ND-mode) ESD stresses.
To meet system-level ESD specifications, some methods are provided to integrate a plurality of discrete noise-decoupling components or board-level noise filters into a CMOS IC product, so as to decouple, bypass, or absorb the electrical transient voltages (energy) under system-level ESD tests. The noise filter circuit, such as a capacitor filter, ferrite bead, transient voltage suppressor (TVS), LC-like (2nd-order), and pi-section (3rd-order) filters, can be used to increase system-level ESD immunity, as shown in FIGS. 1A-1D. In FIGS. 1A-1D, the noise filter circuits 100A-100D are formed by the resistors R and decoupling capacitors C with various structures.
System-level ESD immunity of CMOS ICs under system-level ESD tests can be greatly improved by choosing proper noise filter circuits. Typically, large area/size discrete noise-bypassing components within the noise filter circuits can provide better effect for system-level ESD immunity. However, it is hard to integrate the large discrete components into a single chip due to process limitations, die size requirements, and total cost requirements.
Therefore, to meet high system-level ESD specifications, a chip-level noise filter having strong transient disturbance bypassing capability without requirement a large area is desired.